Event-Driven Embedded System Synthesis

One can argue that hardware design is fast disappearing into the ether of software, especially for embedded systems. Complex algorithms can be synthesized directly into hardware by designers who are ignorant of many of the tradeoffs being made right under their nose. Application-specific engines are synthesized in custom programmable logic and interfaced to embedded soft and hard IP cores in days rather than months. The ability to leverage existing IP allows complex systems to be realized in a fraction the design time and cost. That being said, the vast majority of such systems use fixed hardware designs where the system is composed of and largely exists in custom software and software interfaces. There are several issues with this strategy, the most pressing being system feedback loop delays depend on software timing and time quantization, substantially limiting the possible performance of the system. An alternative tack would be to construct a high level system specification which describes the interaction and control of the system delegating the functional behavior to hardware and software components. In such a scheme, one could synthesize the common specification to numerous implementations that vary hardware and software contributions. These alternative designs would be functionally equivalent, but lie at distinct performance/power/complexity tradeoff points. To this end, we have created a behavior description language with latency-insensitive composition semantics that uniformly addresses hardware and software design. By advocating latencyinsenstivity at all design levels, we simplify maintenance of behavioral correctness to ease the creation of small to medium size embedded systems. This simplification is achieved because design alternatives can be selected locally without fear of introducing behavioral bugs. Although timing and throughput bounds are not inherent in the specificaiton, they can be achieved in particular designs by using bounding arguments particular to the implementation mechanism. Current embedded system languages e.g. Esterel, Signal, SpecC have limited power to create high quality hardware, largely because the underlying semantics assume centralized control with potentially many critical paths. Mechanisms such as broadcast, global variable access, and implicit atomic timing result in implementations where critical paths must be discovered rather than planned. In contrast, our language (TDL) is designed around the basic notion that functionality is encapsulated by latency-independent tasks which are controlled locally by a distributed control scheme. This allows for implementation targets spanning hardware and software designs from a common specification since determination of the locations and latencies of controllers can be performed as part of the synthesis, independent of the behavior and wholly in deference to design performance and cost requirments.